Datasheet
PCA9535A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 11 September 2012 3 of 38
NXP Semiconductors
PCA9535A
Low-voltage 16-bit I
2
C-bus I/O port with interrupt
4. Block diagram
5. Pinning information
5.1 Pinning
Remark: All I/Os are set to inputs at reset.
Fig 1. Block diagram of PCA9535A
PCA9535A
POWER-ON
RESET
002aag207
I
2
C-BUS/SMBus
CONTROL
INPUT
FILTER
SCL
SDA
V
DD
INPUT/
OUTPUT
PORTS
P0_0
V
SS
8-bit
write pulse
read pulse
P0_2
P0_1
P0_3
P0_4
P0_5
P0_6
P0_7
INPUT/
OUTPUT
PORTS
P1_0
8-bit
write pulse
read pulse
P1_2
P1_1
P1_3
P1_4
P1_5
P1_6
P1_7
A1
A0
LP
FILTER
V
DD
INT
A2
Fig 2. Pin configuration for TSSOP24 Fig 3. Pin configuration for HWQFN24
V
DD
SDA
SCL
A0
P1_7
P1_6
P1_5
P1_4
P1_3
P1_2
P1_1
P1_0
INT
A1
A2
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
V
SS
PCA9535APW
002aag208
1
2
3
4
5
6
7
8
9
10
11
12
14
13
16
15
18
17
20
19
22
21
24
23
002aag209
Transparent top view
P1_3
P0_4
P0_5
P1_4
P0_3 P1_5
P0_2 P1_6
P0_1 P1_7
P0_0 A0
P0_6
P0_7
V
SS
P1_0
P1_1
P1_2
A2
A1
INT
V
DD
SDA
SCL
terminal 1
index area
6
13
5
14
4 15
3 16
2 17
1
18
7
8
9
10
11
12
24
23
22
21
20
19
PCA9535AHF