Datasheet

PCA9534_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 6 November 2006 8 of 25
NXP Semiconductors
PCA9534
8-bit I
2
C-bus and SMBus low power I/O port with interrupt
Fig 8. Write to Output Port register
1 0 0 A2 A1 A0 0 AS0
START condition R/W
acknowledge
from slave
002aac472
A
acknowledge
from slave
SCL
SDA A
write to port
data out
from port
P
t
v(Q)
987654321
command byte
acknowledge
from slave
data to port
DATA 1
slave address
00000010
STOP
condition
data 1 valid
Fig 9. Write to Configuration register or Polarity Inversion register
1 0 0 A2 A1 A0 0 AS0
START condition R/W
acknowledge
from slave
002aac473
A
acknowledge
from slave
SCL
SDA A
data to
register
P
987654321
command byte
acknowledge
from slave
data to register
DATA
slave address
0000011/00
STOP
condition
Fig 10. Read from register
1 0 0 A2 A1 A0 0 AS0
START condition R/W
acknowledge
from slave
002aac474
A
acknowledge
from slave
SDA
A P
command byte
acknowledge
from master
data from register
DATA (first byte)
slave address
STOP
condition
S
(repeated)
START condition
(cont.)
(cont.)
1 0 0 A2 A1 A0 1 A0
R/W
acknowledge
from slave
slave address
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
NA
no acknowledge
from master
data from register
DATA (last byte)