Datasheet

PCA9534_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 6 November 2006 7 of 25
NXP Semiconductors
PCA9534
8-bit I
2
C-bus and SMBus low power I/O port with interrupt
6.5 Device address
6.6 Bus transactions
Data is transmitted to the PCA9534 registers using the Write mode as shown in Figure 8
and Figure 9. Data is read from the PCA9534 registers using the Read mode as shown in
Figure 10 and Figure 11. These devices do not implement an auto-increment function, so
once a command byte has been sent, the register which was addressed will continue to
be accessed by reads until a new command byte has been sent.
Remark: At power-on reset, all registers return to default values.
Fig 6. Simplified schematic of IO0 to IO7
V
DD
IO0 to IO7
output port
register data
configuration
register
DQ
CK Q
data from
shift register
write configuration
pulse
output port
register
DQ
CK
write pulse
polarity inversion
register
DQ
CK
data from
shift register
write polarity
pulse
input port
register
DQ
CK
read pulse
input port
register data
polarity inversion
register data
002aac470
FF
data from
shift register
FF
FF
FF
Q1
Q2
V
SS
to INT
Fig 7. PCA9534 device address
002aac471
0 1 0 0 A2 A1 A0 R/W
fixed
slave address
hardware
selectable