Datasheet

PCA9527_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 29 June 2009 14 of 22
NXP Semiconductors
PCA9527
3-channel bidirectional bus extender for HDMI, I
2
C-bus and SMBus
[1] LOW-level supply voltage.
[2] V
IL
specification is for the first LOW level seen by the SDAB/SCLB/CECB lines. V
ILc
is for the second and subsequent LOW levels seen
by the SDAB/SCLB/CECB lines to retain a valid LOW level the static level must be less than V
ILc
.
[3] V
IL
for port A with envelope noise must be below 0.3V
CC(A)
for stable performance.
10. Dynamic characteristics
[1] Times are specified with loads of 1.35 kΩ pull-up resistance and 57 pF load capacitance on port B, and 450 Ω pull-up resistance and
57 pF load capacitance on port A. Different load resistance and capacitance will alter the RC time constant, thereby changing the
propagation delay and transition times.
[2] Pull-up voltages are V
CC(A)
on port A and V
CC(B)
on port B.
[3] Typical values were measured with V
CC(A)
= 3.3 V at T
amb
=25°C, unless otherwise noted.
[4] The t
PLH
delay data from port B to port A is measured at 0.5 V on port B to 0.3V
CC(A)
on port A.
[5] The proportional delay data from port A to port B is measured at 0.3V
CC(A)
on port A to 0.3V
CC(B)
on port B.
[6] The enable pin, EN, should only change state when the global bus and the repeater port are in an idle state.
[7] If the V
CC(A)
ramp up is fast, then the t
rec(pd-act)
time must be allowed before the inputs are switched. If the supply ramp up is slow, the
channels may be connected even before the final supply voltage is reached.
[8] If the V
CC(B)
ramp up is fast, then the t
rec(pd-act)
time must be allowed before the inputs are switched. If the supply ramp up is slow, the
channels may be connected even before the final supply voltage is reached.
Table 6. Dynamic characteristics
V
CC
=2.7V to 5.5V; GND=0V; T
amb
= − 40 ° Cto+85 ° C; unless otherwise specified.
[1][2]
Symbol Parameter Conditions Min Typ
[3]
Max Unit
t
PLH
LOW to HIGH propagation delay port B to port A; Figure 15
[4]
70 115 350 ns
t
PHL
HIGH to LOW propagation delay port B to port A; Figure 13 40 75 180 ns
t
TLH
LOW to HIGH output transition time port A; Figure 13 20 155 280 ns
t
THL
HIGH to LOW output transition time port A; Figure 13 20 60 100 ns
t
PLH
LOW to HIGH propagation delay port A to port B; Figure 14
[5]
125 175 310 ns
t
PHL
HIGH to LOW propagation delay port A to port B; Figure 14
[5]
130 220 330 ns
t
TLH
LOW to HIGH output transition time port B; Figure 14 80 130 260 ns
t
THL
HIGH to LOW output transition time port B; Figure 14 20 45 100 ns
t
PLH
LOW to HIGH propagation delay CECA; Figure 16 40 110 250 ns
t
PHL
HIGH to LOW propagation delay CECA; Figure 16 40 80 180 ns
t
TLH
LOW to HIGH output transition time CECA; Figure 16 80 150 260 ns
t
THL
HIGH to LOW output transition time CECA; Figure 16 20 60 100 ns
t
su
set-up time EN HIGH before START condition
[6]
200 - - µs
t
h
hold time EN HIGH after STOP condition
[6]
200 - - ns
t
rec(pd-act)
recovery time from power-down to
active
V
CC(A)
power-down to active;
EN HIGH and V
CC(B)
on;
V
CC(A)
ramping up
[7]
200 - - µs
V
CC(B)
power-down to active;
EN HIGH and V
CC(A)
on;
V
CC(B)
ramping up
[8]
200 - - µs