Datasheet

PCA9516A_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 23 April 2009 6 of 19
NXP Semiconductors
PCA9516A
5-channel I
2
C-bus hub
The PCA9516A is 5.5 V tolerant so it does not require any additional circuitry to translate
between the different bus voltages.
When one side of the PCA9516A is pulled LOW by a device on the I
2
C-bus, a CMOS
hysteresis type input detects the falling edge and causes an internal driver on the other
side to turn on, thus causing the other side to also go LOW. The side driven LOW by the
PCA9516A will typically be at V
OL
= 0.5 V.
In order to illustrate what would be seen in a typical application, refer to Figure 6 and
Figure 7. If the bus master in Figure 5 were to write to the slave through the PCA9516A,
we would see the waveform shown in Figure 6 on Bus 0. This looks like a normal I
2
C-bus
transmission until the falling edge of the 8
th
clock pulse. At that point, the master releases
the data line (SDA) while the slave pulls it LOW through the PCA9516A. Because the V
OL
of the PCA9516A is typically around 0.5 V, a step in the SDA will be seen. After the master
has transmitted the 9
th
clock pulse, the slave releases the data line.
On the Bus 1 side of the PCA9516A, the clock and data lines would have a positive offset
from ground equal to the V
OL
of the PCA9516A. After the 8
th
clock pulse, the data line will
be pulled to the V
OL
of the slave device that is very close to ground in our example.
It is important to note that any arbitration or clock stretching events on Bus 1 require that
the V
OL
of the devices on Bus 1 be 70 mV below the V
OL
of the PCA9516A (see V
OL
−V
ILc
in Section 9 “Static characteristics”) to be recognized by the PCA9516A and then
transmitted to Bus 0.
Fig 5. Typical application
002aae617
SCL1
SDA1
SLAVE 1
SDA
SCL
400 kHz
5 V
SCL2
SDA2
SLAVE 2
SDA
SCL
400 kHz
3.3 V
SCL3
SDA3
SLAVE 3
SDA
SCL
100 kHz
5 V
SCL4
SDA4
3.3 V or 5 V
PCA9516A
V
CC
SCL0
SDA0
SCL
3.3 V
SDA
EN2
EN1
EN3
EN4
BUS
MASTER
400 kHz