Datasheet
PCA9512A_PCA9512B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 1 March 2013 15 of 27
NXP Semiconductors
PCA9512A; PCA9512B
Level shifting hot swappable I
2
C-bus and SMBus bus buffer
[1] This specification applies over the full operating temperature range.
[2] Card side supply voltage.
[3] The enable time is from power-up of V
CC
and V
CC2
2.7 V to when idle or stop time begins.
[4] Idle time is from when SDAn and SCLn are HIGH after enable time has been met.
[5] I
trt(pu)
varies with temperature and V
CC
voltage, as shown in Section 11.1 “Typical performance characteristics”.
[6] Input pull-up voltage should not exceed power supply voltage in operating mode because the rise time accelerator will clamp the voltage
to the positive supply rail.
[7] The connection circuitry always regulates its output to a higher voltage than its input. The magnitude of this offset voltage as a function
of the pull-up resistor and V
CC
voltage is shown in Section 11.1 “Typical performance characteristics”.
[8] Guaranteed by design, not production tested.
[9] C
b
= total capacitance of one bus line in pF.
Input-output connection
V
offset
offset voltage 10 k to V
CC
on SDA, SCL;
V
CC
=3.3V; V
CC2
=3.3V;
V
I
=0.2V
[1][7]
0 115 175 mV
C
i
input capacitance digital; guaranteed by design,
not subject to test
--10pF
V
OL
LOW-level output voltage V
I
= 0 V; SDAn, SCLn pins;
I
sink
=3mA; V
CC
=2.7V;
V
CC2
=2.7V
[1]
00.30.4V
I
LI
input leakage current SDAn, SCLn pins; V
CC
=5.5V;
V
CC2
=5.5V
1-+1A
System characteristics
f
SCL
SCL clock frequency
[8]
0-400kHz
t
BUF
bus free time between a
STOP and START
condition
[8]
1.3 - - s
t
HD;STA
hold time (repeated)
START condition
[8]
0.6 - - s
t
SU;STA
set-up time for a repeated
START condition
[8]
0.6 - - s
t
SU;STO
set-up time for STOP
condition
[8]
0.6 - - s
t
HD;DAT
data hold time
[8]
300 --ns
t
SU;DAT
data set-up time
[8]
100 --ns
t
LOW
LOW period of the SCL
clock
[8]
1.3 - - s
t
HIGH
HIGH period of the SCL
clock
[8]
0.6 - - s
t
f
fall time of both SDA and
SCL signals
[8][9]
20 + 0.1 C
b
-300ns
t
r
rise time of both SDA and
SCL signals
[8][9]
20 + 0.1 C
b
-300ns
Table 6. Characteristics …continued
V
CC
= 2.7 V to 5.5 V; T
amb
=
40
C to +85
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit