Datasheet

PCA9509A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 17 July 2013 7 of 25
NXP Semiconductors
PCA9509A
Low power level translating I
2
C-bus/SMBus repeater
When the bus capacitance is high, the current should be set near the maximum current
drive for the weakest part. However, if the bus capacitance is low a lower current/higher
resistor value should be used to keep the rise time from getting so fast that it causes
problems. The A side does not need a pull-up resistor. If one is added, care must be taken
to keep the LOW-level voltage at the A side input below 0.1V
CC(A)
.
7. Application design-in information
A typical application is shown in Figure 4. In this example, the CPU is running on a 0.9 V
I
2
C-bus while the slave is connected to a 3.3 V bus. Both buses run at 400 kHz. Master
devices can be placed on either bus.
When port B of the PCA9509A is pulled LOW by a driver on the I
2
C-bus, a CMOS
hysteresis input detects the falling edge when it goes below 0.3V
CC(B)
and causes the
internal driver on port A to turn on, causing port A to pull down to about 0.2V
CC(A)
. When
port A of the PCA9509A falls, a comparator detects the falling edge when it falls below
0.15V
CC(A)
and causes the internal driver on port B to turn on and pull the port B pin down
to ground. In order to illustrate what would be seen in a typical application, refer to
Figure 5
and Figure 6. If the bus master in Figure 4 were to write to the slave through the
PCA9509A, waveforms shown in Figure 5
would be observed on the B bus. This looks
like a normal I
2
C-bus transmission.
On the A bus side of the PCA9509A, the clock and data lines are driven by the master and
swing nearly to ground. After the eighth clock pulse, the slave replies with an ACK that
causes a LOW on the A side equal to the V
OL
of the PCA9509A, which the master
recognizes as a LOW. It is important to note that any arbitration or clock stretching events
require that the LOW level on the A bus side at the input of the PCA9509A (V
IL
) is below
0.1V
CC(A)
to be recognized by the PCA9509A and then transmitted to the B bus side.
Fig 4. Typical application
002aaf973
V
CC(B)
V
CC(A)
PCA9509A
A1 B1
A2 B2
EN
10 kΩ
10 kΩ
SDA
SCL
MASTER
CPU
SLAVE
400 kHz
SDA
SCL
bus A bus B
3.3 V
0.9 V
10 kΩ
0.9 V