Datasheet

PCA9509A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 17 July 2013 6 of 25
NXP Semiconductors
PCA9509A
Low power level translating I
2
C-bus/SMBus repeater
The enable pin should only change state when the bus and the repeater port are in an idle
state to prevent system failures.
Because the enable pin (EN) can put the PCA9509A in Standby mode, and when in
standby the current sources and current mirrors are turned OFF to save power, the
recovery from the disabled/standby state is slow so that the current sources and current
mirrors can return to full current before the channels are enabled.
Remark: The system design should allow sufficient time after STOP before disabling the
PCA9509A so that both sides of the SDA and SCL channels are HIGH. It should also
allow sufficient time before the START such that the channel is disabled before the SDA
goes LOW. The PCA9509A should only be enabled during a bus idle state and there also
must be sufficient time allowed before the START such that the PCA9509A is fully active
before the falling edge of the SDA that defines a START.
6.2 I
2
C-bus systems
As with the standard I
2
C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the buffered bus (standard open-collector configuration of the I
2
C-bus).
The size of these pull-up resistors depends on the system. Each of the port A I/Os has an
internal pull-up current source and does not require the external pull-up resistor. Port B is
designed to work with Standard-mode and Fast-mode I
2
C-bus devices in addition to
SMBus devices. Standard-mode I
2
C-bus devices only specify 3 mA output drive; this
limits the termination current to 3 mA in a generic I
2
C-bus system where Standard-mode
devices and multiple masters are possible. Under certain conditions higher termination
currents can be used.
6.3 Edge rate control
The PCA9509A includes circuitry that slows down the falling edge of both the A side and
B side open-drain output pull-downs. This slowdown reduces system noise and
undershoot when the signal reflects off of the end of the bus. The slew rate control circuit
limits the maximum slew rate, and is relatively insensitive to the load capacitance, the bus
high voltage and to the pull-up value. The rising edge slew rate on the A side is controlled
by the pull-up current source and the load capacitance. The rising edge slew rate on the
B side is controlled by RC time constant of the bus pull-up resistor and the bus
capacitance, which are system level considerations and not under the control of the
PCA9509A. The B side pull-up resistor should be chosen based on the total B side bus
capacitance to result in a reasonable rising edge transition time that is less than the
maximum allowed rise time, and slow enough not to make system level noise problems.
6.4 Bus pull-up resistor selection
The AC test load for the B side of the PCA9509A is 1.35 k and 50 pF total capacitance.
This results in a rise time of approximately 60 ns. The 1.35 k resistor is chosen to
provide a little less than 3 mA in a 3.3 V application so it is compatible with
Standard-mode I
2
C-bus devices as well as Fast-mode devices. The B side output
pull-down is a strong driver and is capable of sinking Fast-mode Plus (Fm+) currents,
however the pull-up must be sized for the weakest part in the system, so if Standard-mode
I
2
C-bus parts are present on the B side, the pull-up must be limited to less than 3 mA. If
only Fm+ parts are used on the B side, the maximum pull-up current may be up to 30 mA.
The pull-up resistor should always be sized to provide less than the rated pull-up current
for the weakest part on the bus under the maximum bus voltage expected in the system.