Datasheet
PCA9508_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 28 April 2008 4 of 21
NXP Semiconductors
PCA9508
Hot swappable level translating I
2
C-bus repeater
5. Pinning information
5.1 Pinning
5.2 Pin description
6. Functional description
Refer to Figure 1 “Functional diagram of PCA9508”.
The PCA9508 enables I
2
C-bus or SMBus translation down to V
CC(A)
as low as 0.9 V
without degradation of system performance. The PCA9508 contains two bidirectional
open-drain buffers specifically designed to provide superior hot-swap and/or support
up-translation/down-translation between the low voltage (as low as 0.9 V) and a 3.3 V or
5VI
2
C-bus or SMBus. All inputs and I/Os are overvoltage tolerant to 5.5 V even when the
device is unpowered (V
CC(B)
and/or V
CC(A)
= 0 V). The PCA9508 includes a power-up
circuit that keeps the output drivers turned off until V
CC(B)
is above 2.5 V and the V
CC(A)
is
above 0.8 V. V
CC(B)
and V
CC(A)
can be applied in any sequence at power-up. V
CC(A)
is only
used to provide the 0.5V
CC(A)
reference to the A side input comparators and for the power
good detect circuit. The PCA9508 logic and all I/Os are powered by the V
CC(B)
pin.
An undervoltage/initialization circuit holds the PCA9508 in a disconnected state which
presents high-impedance to all SDA and SCL pins during power-up. A LOW on the enable
pin (EN) also forces the parts into the disconnected state. As the power supply is brought
up and EN is HIGH or the part is powered and EN is taken from LOW to HIGH it enters an
initialization state where the internal references are stabilized. At the end of the
initialization state the ‘STOP bit and bus idle’ detect circuit is enabled. With the EN pin
Fig 2. Pin configuration for SO8 Fig 3. Pin configuration for TSSOP8
PCA9508D
V
CC(A)
V
CC(B)
SCLA SCLB
SDAA SDAB
GND EN
002aac652
1
2
3
4
6
5
8
7
PCA9508DP
V
CC(A)
V
CC(B)
SCLA SCLB
SDAA SDAB
GND EN
002aac653
1
2
3
4
6
5
8
7
Table 3. Pin description
Symbol Pin Description
V
CC(A)
1 A side supply voltage (0.9 V to 5.5 V)
SCLA 2 open-drain input/output serial clock A side bus
SDAA 3 open-drain input/output serial data A side bus
GND 4 supply ground (0 V)
EN 5 active HIGH repeater enable input with an internal pull-up (100 kΩ)
SDAB 6 open-drain input/output serial data B side bus
SCLB 7 open-drain input/output serial clock B side bus
V
CC(B)
8 B side supply voltage (2.7 V to 5.5 V)