Datasheet

PCA9507_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 7 February 2008 3 of 20
NXP Semiconductors
PCA9507
2-wire serial bus extender for HDMI DDC I
2
C-bus and SMBus
5. Pinning information
5.1 Pinning
5.2 Pin description
6. Functional description
Refer to Figure 1 “Functional diagram of PCA9507”.
The PCA9507 consists of a pair of bidirectional open-drain I/Os specifically designed to
support up-translation/down-translation between low voltages (as low as 2.7 V) and a
3.3 V or 5 V I
2
C-bus and SMBus. The device contains a rise time accelerator on port A
that enables the device to drive a long cable or a heavier capacitive load for DDC, I
2
C-bus
and SMBus applications. With dual supply rails, the device translates from voltage ranges
2.7 V to 5.5 V down to a voltage as low as 2.7 V without degradation of system
performance. All I/Os are overvoltage tolerant to 5.5 V even when the device is
un-powered (V
CC(B)
and/or V
CC(A)
= 0 V).
The PCA9507 includes a power-up circuit that keeps the output drivers turned off until
V
CC(A)
and V
CC(B)
rise above 2.7 V. V
CC(A)
and V
CC(B)
can be applied in any sequence at
power-up.
Fig 2. Pin configuration for SO8 Fig 3. Pin configuration for TSSOP8
PCA9507D
V
CC(A)
V
CC(B)
SCLA SCLB
SDAA SDAB
GND EN
002aad399
1
2
3
4
6
5
8
7
PCA9507DP
V
CC(A)
V
CC(B)
SCLA SCLB
SDAA SDAB
GND EN
002aad400
1
2
3
4
6
5
8
7
Table 2. Pin description
Symbol Pin Description
V
CC(A)
1 port A supply voltage (2.7 V to 5.5 V)
SCLA 2 serial clock port A bus with rise time accelerator for DDC line or cable,
5 V tolerant
SDAA 3 serial data port A bus with rise time accelerator for DDC line or cable,
5 V tolerant
GND 4 supply ground (0 V)
EN 5 active HIGH buffer enable input
SDAB 6 serial data port B bus with static level offset, 5 V tolerant
SCLB 7 serial clock port B bus with static level offset, 5 V tolerant
V
CC(B)
8 port B supply voltage (2.7 V to 5.5 V)