Datasheet

PCA9501_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 10 February 2009 3 of 28
NXP Semiconductors
PCA9501
8-bit I
2
C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM
5. Block diagram
6. Pinning information
6.1 Pinning
Fig 1. Block diagram of PCA9501
PCA9501
POWER-ON
RESET
002aac000
V
SS
V
DD
I
2
C-BUS/SMBus
CONTROL
INPUT
FILTER
SCL
SDA
A0
INT
8-bit
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
INPUT/
OUTPUT
PORTS
write pulse
read pulse
LP
FILTER
300 kΩ
A1
A2
A3
A4
A5
EEPROM
256 × 8
WC
V
DD
Fig 2. Pin configuration for SO20 Fig 3. Pin configuration for TSSOP20
PCA9501D
A0 V
DD
A1 SDA
A2 SCL
IO0 WC
IO1 IO7
IO2 IO6
IO3 IO5
INT IO4
A5 A3
V
SS
A4
002aab997
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
A0 V
DD
A1 SDA
A2 SCL
IO0 WC
IO1 IO7
IO2 IO6
IO3 IO5
INT IO4
A5 A3
V
SS
A4
PCA9501PW
002aab998
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19