Datasheet
PCA9500_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 15 April 2009 9 of 26
NXP Semiconductors
PCA9500
8-bit I
2
C-bus and SMBus I/O port with 2-kbit EEPROM
7.4.2.2 Random read
The PCA9500's random read mode allows the address to be read from to be specified by
the master. This is done by performing a dummy write to set the address counter to the
location to be read. The master must perform a byte write to the address location to be
read, but instead of transmitting the data after receiving the acknowledge from the
PCA9500, the master re-issues the START condition and memory slave address with the
R/W bit set to one. The PCA9500 will then transmit an acknowledge and use the next
eight clock cycles to transmit the data contained in the addressed location. The master
ceases the transmission by issuing the STOP condition after the eighth bit, omitting the
ninth clock cycle acknowledge.
7.4.2.3 Sequential read
The PCA9500 sequential read is an extension of either the current address read or
random read. If the master does not issue a STOP condition after it has received the
eighth data bit, but instead issues an acknowledge, the PCA9500 will increment the
address counter and use the next eight cycles to transmit the data from that location. The
master can continue this process to read the contents of the entire memory. Upon
reaching address 255 the counter will return to address 0 and continue transmitting data
until a STOP condition is received. The master ceases the transmission by issuing the
STOP condition after the eighth bit, omitting the ninth clock cycle acknowledge.
Fig 12. Current address read
1 AS
slave address (memory)
START condition R/W acknowledge
from slave
002aae596
data from memory
SDA 0 1 0 A2 A1 A01 P
STOP condition
Fig 13. Random read
0 AS
slave address (memory)
START condition R/W acknowledge
from slave
002aae597
word address
SDA 0 1 0 A2 A1 A01 P
STOP
condition
A
acknowledge
from slave
data from memory
A
acknowledge
from slave
1S
slave address (memory)
START condition R/W
0 1 0 A2 A1 A01
Fig 14. Sequential read
1 AS
slave address (memory)
START condition R/W acknowledge
from slave
002aae598
data from memory
SDA 0 1 0 A2 A1 A01 P
STOP
condition
A
acknowledge
from master
data from memory
DATA n
data from memory
DATA n + 1 A
acknowledge
from master
DATA n + X