Datasheet

PCA9500_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 15 April 2009 5 of 26
NXP Semiconductors
PCA9500
8-bit I
2
C-bus and SMBus I/O port with 2-kbit EEPROM
7. Functional description
Refer also to Figure 1 “Block diagram of PCA9500”.
7.1 Device addressing
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9500 is shown in Figure 6. Internal pull-up resistors
are incorporated on the hardware selectable address pins.
The last bit of the address byte defines the operation to be performed. When set to logic 1
a read is selected, while a logic 0 selects a write operation.
7.2 Control register
The PCA9500 contains a single 8-bit register called the Control register, which can be
written and read via the I
2
C-bus. This register is sent after a successful acknowledgment
of the slave address. It contains the I/O operation information.
Fig 5. Simplified schematic diagram of each I/O
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write pulse
read pulse
D
CI
S
FF
Q
power-on reset
data from shift register
100 µA
V
DD
IO0 to IO7
V
SS
D
CI
S
FF
Q
data to shift register
to interrupt logic
a. I/O expander b. Memory
Fig 6. PCA9500 slave addresses
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0 1 0 0 A2 A1 A0 R/W
fixed
slave address
hardware
programmable
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1 0 1 0 A2 A1 A0 R/W
fixed
slave address
hardware
programmable