Datasheet

PCA9500_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 15 April 2009 4 of 26
NXP Semiconductors
PCA9500
8-bit I
2
C-bus and SMBus I/O port with 2-kbit EEPROM
6.2 Pin description
[1] HVQFN16 package supply ground is connected to both V
SS
pin and exposed center pad. V
SS
pin must be
connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level
performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the
board and for proper heat conduction through the board, thermal vias need to be incorporated in the
printed-circuit board in the thermal pad region.
Fig 4. Pin configuration for HVQFN16
SCL
WC
IO7
IO6
002aae584
PCA9500BS
Transparent top view
IO3
V
SS
IO4
IO5
A1 A2 V
DD
SDA
4 9
3 10
2 11
1 12
5 6
7
8
16 15 14 13
terminal 1
index area
A2
IO0
IO1
IO2
Table 3. Pin description
Symbol Pin Description
SO16, TSSOP16 HVQFN16
A0 1 15 address lines (internal pull-up)
A1 2 16
A2 3 1
IO0 4 2 quasi-bidirectional I/O pins
IO1 5 3
IO2 6 4
IO3 7 5
IO4 9 7
IO5 10 8
IO6 11 9
IO7 12 10
V
SS
86
[1]
supply ground
WC 13 11 active LOW write control pin
SCL 14 12 I
2
C-bus serial clock
SDA 15 13 I
2
C-bus serial data
V
DD
16 14 supply voltage