Datasheet

PCA9500_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 15 April 2009 3 of 26
NXP Semiconductors
PCA9500
8-bit I
2
C-bus and SMBus I/O port with 2-kbit EEPROM
5. Block diagram
6. Pinning information
6.1 Pinning
Fig 1. Block diagram of PCA9500
PCA9500
POWER-ON
RESET
002aae585
V
SS
V
DD
I
2
C-BUS/SMBus
CONTROL
INPUT
FILTER
SCL
SDA
8-bit
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
INPUT/
OUTPUT
PORTS
write pulse
read pulse
300 kΩ
A0
A1
A2
EEPROM
256 × 8
WC
Fig 2. Pin configuration for SO16 Fig 3. Pin configuration for TSSOP16
PCA9500D
A0 V
DD
A1 SDA
A2 SCL
IO0 WC
IO1 IO7
IO2 IO6
IO3 IO5
V
SS
IO4
002aae582
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
V
DD
SDA
SCL
WC
IO7
IO6
IO5
IO4
A0
A1
A2
IO0
IO1
IO2
IO3
V
SS
PCA9500PW
002aae583
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15