Datasheet

PCA9500_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 15 April 2009 17 of 26
NXP Semiconductors
PCA9500
8-bit I
2
C-bus and SMBus I/O port with 2-kbit EEPROM
Fig 22. I
2
C-bus timing
SCL
SDA
t
HD;STA
t
SU;DAT
t
HD;DAT
t
f
t
BUF
t
SU;STA
t
LOW
t
HIGH
t
VD;ACK
002aab175
t
SU;STO
protocol
START
condition
(S)
bit 7
MSB
(A7)
bit 6
(A6)
bit 0
(R/W)
acknowledge
(A)
STOP
condition
(P)
1
/f
SCL
t
r
t
VD;DAT
Fig 23. Write cycle timing
002aad310
STOP
condition
START
condition
T
cy(W)
ACK8
th
bit
word n
SCL
SDA
memory
address