Datasheet

PCA9500_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 15 April 2009 12 of 26
NXP Semiconductors
PCA9500
8-bit I
2
C-bus and SMBus I/O port with 2-kbit EEPROM
9. Application design-in information
A central processor/controller typically located on the system main board can use the
400 kHz I
2
C-bus/SMBus to poll the PCA9500 devices located on the system cards for
status or version control type of information. The PCA9500 may be programmed at
manufacturing to store information regarding board build, firmware version, manufacturer
identification, configuration option data, and so on. Alternately, these devices can be used
as convenient interface for board configuration, thereby utilizing the I
2
C-bus/SMBus as an
intra-system communication bus.
Fig 19. PCA9500 used as interface for board configuration
I
2
C-bus
I
2
C-bus
I
2
C-bus
I
2
C-bus
ASIC
GPIO
CONTROL
EEPROM
monitoring
and
control
configuration control
PCA9500
INPUTS
ALARM
LEDs
I
2
C-bus
card ID, subroutines, configuration data, or revision history
up to
8 cards
BACKPLANE
I
2
C-bus
CPU
OR
µC
002aae586