Datasheet

PCA8574_PCA8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 3 June 2013 5 of 32
NXP Semiconductors
PCA8574; PCA8574A
Remote 8-bit I/O expander for I
2
C-bus with interrupt
6.2 Pin description
7. Functional description
Refer to Figure 1 “Block diagram”.
7.1 Device address
Following a START condition, the bus master must send the address of the slave it is
accessing and the operation it wants to perform (read or write). The address format of the
PCA8574/74A is shown in Figure 6
. Slave address pins A2, A1 and A0 are held HIGH or
LOW to choose one of eight slave addresses. To conserve power, no internal pull-up
resistors are incorporated on pins A2, A1, or A0 so they must be externally held HIGH or
LOW. The address pins (A2, A1, A0) can connect to V
DD
or V
SS
directly or through
resistors.
Table 3. Pin description
Symbol Pin Description
DIP16, SO16 SSOP20
A0 1 6 address input 0
A1 2 7 address input 1
A2 3 9 address input 2
P0 4 10 quasi-bidirectional I/O 0
P1 5 11 quasi-bidirectional I/O 1
P2 6 12 quasi-bidirectional I/O 2
P3 7 14 quasi-bidirectional I/O 3
V
SS
8 15 supply ground
P4 9 16 quasi-bidirectional I/O 4
P5 10 17 quasi-bidirectional I/O 5
P6 11 19 quasi-bidirectional I/O 6
P7 12 20 quasi-bidirectional I/O 7
INT
13 1 interrupt output (active LOW)
SCL 14 2 serial clock line
SDA 15 4 serial data line
V
DD
16 5 supply voltage
n.c. - 3, 8, 13, 18 not connected
a. PCA8574 b. PCA8574A
Fig 6. PCA8574 and PCA8574A slave addresses
R/W
002aah469
0 1 0 0 A2 A1 A0
hardware
selectable
slave address
0
fixed
R/W
002aah470
0 1 1 1 A2 A1 A0
hardware
selectable
slave address
0
fixed