Datasheet

PCA8574_PCA8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 3 June 2013 28 of 32
NXP Semiconductors
PCA8574; PCA8574A
Remote 8-bit I/O expander for I
2
C-bus with interrupt
19. Abbreviations
20. Revision history
Table 13. Abbreviations
Acronym Description
CDM Charged-Device Model
CMOS Complementary Metal Oxide Semiconductor
ESD ElectroStatic Discharge
FF Flip-Flop
GPIO General Purpose Input/Output
HBM Human Body Model
I/O Input/Output
I
2
C-bus Inter-Integrated Circuit bus
IC Integrated Circuit
LED Light Emitting Diode
LP Low-Pass
LSB Least Significant Bit
MSB Most Significant Bit
PLC Programmable Logic Controller
POR Power-On Reset
SMBus System Management Bus
Table 14. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PCA8574_PCA8574A v.3 20130603 Product data sheet - PCA8574_PCA8574A v.2
Modifications:
• Section 1 “General description” re-written
• Section 2 “Features and benefits”
– added (new) first bullet item
– appended “(Fast-mode I
2
C-bus)” to second bullet item
– added (new) third bullet item
– (new) fifth bullet item changed from “50 mA sink capability” to “25 mA sink capability”
– deleted (old) eighth bullet item, “Readable device ID (manufacturer, device type, and
revision)”
– 12th bullet item: deleted phrase “200 V MM per JESD22-A115”
– 14th bullet item: deleted “DIP16”
• Table 1 “Ordering information”:
– deleted discontinued DIP16 package option (PCA8574N, PCA8574AN)
– Topside mark for PCA8574ATS corrected from “PCA8574A” to “PA8574A”
– added Table note [1]
, Table note [2], Table note [3] and Table note [4]
• Added (new) Table 2 “Ordering options”
• Figure 1 “Block diagram” modified: switched positions of blocks “INTERRUPT LOGIC” and
“LP FILTER”
• Figure 2 “Simplified schematic diagram of P0 to P7” modified: removed diode between
“V
DD
” and “P0 to P7” signal lines