Datasheet
PCA8574_PCA8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 3 June 2013 17 of 32
NXP Semiconductors
PCA8574; PCA8574A
Remote 8-bit I/O expander for I
2
C-bus with interrupt
14. Dynamic characteristics
[1] t
VD;ACK
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2] t
VD;DAT
= minimum time for SDA data out to be valid following SCL LOW.
[3] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V
IL
of the SCL signal) in order to
bridge the undefined region SCL’s falling edge.
[4] The maximum t
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t
f
is specified at
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified t
f
.
[5] C
b
= total capacitance of one bus line in pF.
[6] Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
Table 10. Dynamic characteristics
V
DD
= 2.3 V to 5.5 V; V
SS
=0V; T
amb
=
40
Cto+85
C; unless otherwise specified. Limits are for Fast-mode I
2
C-bus.
Symbol Parameter Conditions Min Typ Max Unit
f
SCL
SCL clock frequency 0 - 400 kHz
t
BUF
bus free time between a STOP and START
condition
1.3 - - s
t
HD;STA
hold time (repeated) START condition 0.6 - - s
t
SU;STA
set-up time for a repeated START condition 0.6 - - s
t
SU;STO
set-up time for STOP condition 0.6 - - s
t
HD;DAT
data hold time 0 - - ns
t
VD;ACK
data valid acknowledge time
[1]
0.1 - 0.9 s
t
VD;DAT
data valid time
[2]
50 --ns
t
SU;DAT
data set-up time 100 - - ns
t
LOW
LOW period of the SCL clock 1.3 - - s
t
HIGH
HIGH period of the SCL clock 0.6 - - s
t
f
fall time of both SDA and SCL signals
[3][4]
20 + 0.1C
b
[5]
- 300 ns
t
r
rise time of both SDA and SCL signals 20 + 0.1C
b
[5]
- 300 ns
t
SP
pulse width of spikes that must be
suppressed by the input filter
[6]
- - 50 ns
Port timing; C
L
100 pF (see Figure 8 and Figure 9)
t
v(Q)
data output valid time - - 4 s
t
su(D)
data input set-up time 0 - - s
t
h(D)
data input hold time 4 - - s
Interrupt timing; C
L
100 pF (see Figure 8 and Figure 9)
t
v(INT)
valid time on pin INT from port to INT --4s
t
rst(INT)
reset time on pin INT from SCL to INT --4s