Datasheet

PCA8565 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 5 December 2014 7 of 48
NXP Semiconductors
PCA8565
Real time clock/calendar
8.2 Control registers
8.2.1 Register Control_1
[1] Default value.
[2] Bits labeled as N should always be written with logic 0.
8.2.2 Register Control_2
[1] Bits labeled as N should always be written with logic 0.
[2] Default value.
Table 6. Register Control_1 (address 00h) bits description
Bit Symbol Value Description
7TEST1 0
[1]
normal mode
1 EXT_CLK test mode
6N 0
[2]
default value
5STOP 0
[1]
RTC source clock runs
1 all RTC divider chain flip-flops are asynchronously set to
logic 0;
the RTC clock is stopped (CLKOUT at 32.768 kHz is still
available)
4N 0
[2]
default value
3 TESTC 0 power-on reset override facility is disabled;
set to logic 0 for normal operation
1
[1]
power-on reset override may be enabled
2to0 N 000
[2]
default value
Table 7. Register Control_2 (address 01h) bits description
Bit Symbol Value Description
7to5 N 000
[1]
default value
4TI_TP 0
[2]
INT is active when TF is active (subject to the status of
TIE)
1INT
pulses active according to Table 29 (subject to the
status of TIE);
Remark: note that if AF and AIE are active then INT
will
be permanently active
3AF 0
[2]
alarm flag inactive
1 alarm flag active
2TF 0
[2]
timer flag inactive
1 timer flag active
1AIE 0
[2]
alarm interrupt disabled
1 alarm interrupt enabled
0TIE 0
[2]
timer interrupt disabled
1 timer interrupt enabled