Datasheet

PCA8565 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 5 December 2014 25 of 48
NXP Semiconductors
PCA8565
Real time clock/calendar
9.5.3 Interface watchdog timer
During read/write operations, the time counting circuits are frozen. To prevent a situation
where the accessing device becomes locked and does not clear the interface, the
PCA8565 has a built in watchdog timer. Should the interface be active for more than 1 s
from the time a valid slave address is transmitted, then the PCA8565 will automatically
clear the interface and allow the time counting circuits to continue counting. Under a
correct data transfer, the watchdog timer is stopped on receipt of a START or STOP
condition.
The watchdog is implemented to prevent the excessive loss of time due to interface
access failure e.g. if main power is removed from a battery backed-up system during an
interface access.
Each time the watchdog period is exceeded, 1 s will be lost from the time counters. The
watchdog will trigger between 1 s and 2 s after receiving a valid slave address.
Fig 18. Master reads after setting word address (write word address; read data)
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