Datasheet
PCA8565 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 5 December 2014 24 of 48
NXP Semiconductors
PCA8565
Real time clock/calendar
9.5 I
2
C-bus protocol
9.5.1 Addressing
Before any data is transmitted on the I
2
C-bus, the device which should respond is
addressed first. The addressing is always carried out with the first byte transmitted after
the start procedure.
The PCA8565 acts as a slave receiver or slave transmitter. Therefore the clock signal
SCL is only an input signal, but the data signal SDA is a bidirectional line.
The PCA8565 slave address is shown in Figure 16
.
9.5.2 Clock and calendar read/write cycles
The I
2
C-bus configuration for the different PCA8565 read and write cycles is shown in
Figure 17
, Figure 18 and Figure 19. The word address is a 4-bit value that defines which
register is to be accessed next. The upper four bits of the word address are not used.
Fig 16. Slave address
PFH
5:
JURXS
JURXS
Fig 17. Master transmits to slave receiver (write mode)
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DFNQRZOHGJHPHQW
IURPVODYH
DFNQRZOHGJHPHQW
IURPVODYH
DFNQRZOHGJHPHQW
IURPVODYH
5:
DXWRLQFUHPHQW
PHPRU\ZRUGDGGUHVV
PEG
QE\WHV