Datasheet

PCA6408A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 27 September 2012 9 of 40
NXP Semiconductors
PCA6408A
Low-voltage, 8-bit I
2
C-bus and SMBus I/O expander
7.5 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a
high-impedance input. The input voltage may be raised above V
DD
to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the
Output port register. In this case, there are low-impedance paths between the I/O pin and
either V
DD(P)
or V
SS
. The external voltage applied to this I/O pin should not exceed the
recommended levels for proper operation.
On power-up or reset, all registers return to default values.
Fig 7. Simplified schematic of P0 to P7
V
DD(P)
P0 to P7
output port
register data
configuration
register
DQ
CK Q
data from
shift register
write
configuration
pulse
output port
register
DQ
CK
write pulse
polarity
inversion
register
DQ
CK
data from
shift register
write polarity
pulse
input port
register
DQ
CK
read pulse
input port
register data
polarity
inversion
register data
002aaf824
FF
data from
shift register
FF
FF
FF
Q1
Q2
V
SS
to INT
ESD
protection
diode