Datasheet

PCA6408A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 27 September 2012 8 of 40
NXP Semiconductors
PCA6408A
Low-voltage, 8-bit I
2
C-bus and SMBus I/O expander
7.4 Register descriptions
7.4.1 Input port register (00h)
The Input port register (register 0) reflects the incoming logic levels of the pins, regardless
of whether the pin is defined as an input or an output by the Configuration register. The
Input port register is read only; writes to this register have no effect. The default value ‘X’
is determined by the externally applied logic level. An Input port register read operation is
performed as described in Section 8.2 “
Read commands”.
7.4.2 Output port register (01h)
The Output port register (register 1) shows the outgoing logic levels of the pins defined as
outputs by the Configuration register. Bit values in these registers have no effect on pins
defined as inputs. In turn, reads from this register reflect the value that was written to this
register, not the actual pin value.
7.4.3 Polarity inversion register (02h)
The Polarity inversion register (register 2) allows polarity inversion of pins defined as
inputs by the Configuration register. If a bit in this register is set (written with ‘1’), the
corresponding port pin’s polarity is inverted. If a bit in this register is cleared (written with a
‘0’), the corresponding port pin’s original polarity is retained.
7.4.4 Configuration register (03h)
The Configuration register (register 3) configures the direction of the I/O pins. If a bit in this
register is set to 1, the corresponding port pin is enabled as a high-impedance input. If a
bit in this register is cleared to 0, the corresponding port pin is enabled as an output.
Table 7. Input port register (address 00h)
Bit 7 6 5 4 3 2 1 0
Symbol I7 I6 I5 I4 I3 I2 I1 I0
Default XXXXXXXX
Table 8. Output port register (address 01h)
Bit 7 6 5 4 3 2 1 0
Symbol O7 O6 O5 O4 O3 O2 O1 O0
Default 11111111
Table 9. Register 2: Polarity inversion register (address 02h)
Bit 7 6 5 4 3 2 1 0
Symbol N7 N6 N5 N4 N3 N2 N1 N0
Default 00000000
Table 10. Register 3: Configuration register (address 03h)
Bit 7 6 5 4 3 2 1 0
Symbol C7 C6 C5 C4 C3 C2 C1 C0
Default 11111111