Datasheet

PCA6408A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 27 September 2012 15 of 40
NXP Semiconductors
PCA6408A
Low-voltage, 8-bit I
2
C-bus and SMBus I/O expander
[1] Level that V
DD(P)
can glitch down to with a ramp rate of 0.4 s/V, but not cause a functional disruption when t
w(gl)VDD
<1s.
[2] Glitch width that will not cause a functional disruption when V
DD(gl)
=0.5 V
DD(P)
.
Glitches in the power supply can also affect the power-on reset performance of this
device. The glitch width (t
w(gl)VDD
) and glitch height (V
DD(gl)
) are dependent on each
other. The bypass capacitance, source impedance, and device impedance are factors that
affect power-on reset performance. Figure 17
and Table 11 provide more information on
how to measure these specifications.
V
POR
is critical to the power-on reset. V
POR
is the voltage level at which the reset condition
is released and all the registers and the I
2
C-bus/SMBus state machine are initialized to
their default states. The value of V
POR
differs based on the V
DD(P)
being lowered to or from
0V. Figure 18
and Table 11 provide more details on this specification.
Table 11. Recommended supply sequencing and ramp rates
T
amb
=25  C (unless otherwise noted). Not tested; specified by design.
Symbol Parameter Condition Min Typ Max Unit
(dV/dt)
f
fall rate of change of voltage Figure 15 0.1 - 2000 ms
(dV/dt)
r
rise rate of change of voltage Figure 15 0.1 - 2000 ms
t
d(rst)
reset delay time Figure 15; re-ramp time when
V
DD(P)
drops to V
SS
1- - s
Figure 16
; re-ramp time when
V
DD(P)
drops to V
POR(min)
 50 mV
1- - s
V
DD(gl)
glitch supply voltage difference Figure 17
[1]
--1.0V
t
w(gl)VDD
supply voltage glitch pulse width Figure 17
[2]
--10s
V
POR(trip)
power-on reset trip voltage falling V
DD(P)
0.7--V
rising V
DD(P)
--1.4V
Fig 17. Glitch width and glitch height
Fig 18. Power-on reset voltage (V
POR
)
002aag962
V
DD(P)
time
t
w(gl)VDD
∆V
DD(gl)
002aag963
POR
time
V
DD(P)
time
V
POR
(rising V
DD(P)
)
V
POR
(falling V
DD(P)
)