Datasheet

PCA6408A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 27 September 2012 12 of 40
NXP Semiconductors
PCA6408A
Low-voltage, 8-bit I
2
C-bus and SMBus I/O expander
8.2 Read commands
To read data from the PCA6408A, the bus master must first send the PCA6408A address
with the least significant bit set to a logic 0 (see Figure 5
for device address). The
command byte is sent after the address and determines which register is to be accessed.
After a restart the device address is sent again, but this time the LSB is set to a logic 1.
Data from the register defined by the command byte then is sent by the PCA6408A (see
Figure 10
and Figure 11).
Data is clocked into the register on the rising edge of the ACK clock pulse. There is no
limit on the number of data bytes received in one read transmission, but on the final byte
received the bus master must not acknowledge the data.
Fig 10. Read from register
AS
START condition R/W
acknowledge
from slave
002aaf827
A
acknowledge
from slave
SDA
A P
acknowledge
from master
DATA (first byte)
slave address
STOP
condition
S
(repeated)
START condition
(cont.)
(cont.)
10000
AD
DR
1 A0
R/W
acknowledge
from slave
slave address
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
NA
no acknowledge
from master
10000
AD
DR
0 0
data from register
DATA (last byte)
data from register
command byte
000000 1 1/0
Transfer of data can be stopped at any time by a STOP condition. When this occurs, data present at the latest acknowledge
phase is valid (output mode). It is assumed that the command byte has previously been programmed with 00h (read Input port
register).
This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and
actual data transfer from P port (see Figure 10
).
Fig 11. Read Input port register
10000
AD
DR
1 AS0
slave address
START condition R/W acknowledge from slave
002aaf828
data from port
A
acknowledge from master
SDA 1
no acknowledge
from master
read from
port
data into
port
data from port
DATA 1
DATA 4
INT
DATA 4
DATA 2
DATA 3
P
STOP
condition
t
v(INT)
t
rst(INT)
t
h(D)
t
su(D)
12345678SCL 9
DATA 1 DATA 5
INT is cleared by
read from port
STOP not needed
to clear INT