Datasheet

PCA24S08A_1 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 01 — 19 January 2010 7 of 24
NXP Semiconductors
PCA24S08A
1024 × 8-bit CMOS EEPROM with access protection
6.3 Read operations
Read operations are initiated in the same manner as write operations with the exception
that the LSB of the slave address is set to logic 1.
The lower 7 bits of the word address are incremented after each transmission of a data
byte during a read. The three MSBs of the word address are not changed when the word
counter overflows. Thus, the word address overflows from 127 to 0, and from 255 to 128.
After the read of the last byte within a block, the internal serial address wraps around to
point at the beginning of that block.
Fig 7. Page write operation (16 bytes)
0 1 0 1 B2 B1 0 AS 1 A
START condition
R/W acknowledge
from slave
acknowledge
from slave
word address
A
acknowledge
from slave
word
address
P2 P1 P0 A3 A2 A1 A0B0 DATA A
acknowledge
from slave
DATA + 1
auto-increment
word address
auto-increment
word address
(cont.)
(cont.)
P
STOP condition
A
acknowledge
from slave
DATA + 15
auto-increment
word address
last byte
002aae79
2
Fig 8. Master reads PCA24S08A slave after setting word address (write word address: read data);
sequential read
0 1 0 1 B2 B1 0 AS 1 A
START condition
R/W acknowledge
from slave
acknowledge
from slave
word address
second part
word address
first part
P2 P1 P0 A3 A2 A1 A0B0
DATA
(cont.)
(cont.)
P
STOP condition
A
no acknowledge
from master
DATA
auto-increment
word address
last byte
002aae79
3
S
ReSTART
condition
0101XX11
R/W
A
at this moment master transmitter becomes
master receiver and EEPROM slave transmitter
n bytes
A
auto-increment
word address
acknowledge
from master
acknowledge
from master