Datasheet

PCA24S08A_1 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 01 — 19 January 2010 5 of 24
NXP Semiconductors
PCA24S08A
1024 × 8-bit CMOS EEPROM with access protection
Figure 6 shows how the memory array is addressed when the slave address byte and
address field byte are sent. The master terminates the transfer by generating a STOP
condition. After this STOP condition, the Erase/Write (E/W) cycle starts and the I
2
C-bus is
free for another transmission. Up to 16 bytes of data can be written in the slave writing
sequence (E/W cycle).
Fig 5. Memory addressing
002aae79
0
10101B2B1R/W
fixed
block number
B0 P2 P1 P0 A3 A2 A1 A0
page
number
byte
address
1 1 1 1
BYTE 15
0 0 0 0
BYTE 0
0 0 0
PAGE 0
1 1 1 1
BYTE 15
0 0 0 0
BYTE 0
1 1 1
PAGE 7
1 1 1
BLOCK 7
1 1 1 1
BYTE 15
0 0 0 0
BYTE 0
0 0 0
PAGE 0
1 1 11
BYTE 15
0 0 0 0
BYTE 0
1 1 1
PAGE 7
0 0 0
BLOCK 0