Datasheet

PCA24S08A_1 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 01 — 19 January 2010 15 of 24
NXP Semiconductors
PCA24S08A
1024 × 8-bit CMOS EEPROM with access protection
9. Dynamic characteristics
[1] t
VD;ACK
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2] t
VD;DAT
= minimum time for SDA data out to be valid following SCL LOW.
[3] C
b
= total capacitance of one bus line in pF.
Table 8. Dynamic characteristics
C
L
= 1 TTL gate and 100 pF, except as noted. V
DD
= 2.5 V to 3.6 V.
Symbol Parameter Conditions Standard-mode
I
2
C-bus
Fast-mode I
2
C-bus Unit
Min Max Min Max
f
SCL
SCL clock frequency 0 100 0 400 kHz
t
BUF
bus free time between a STOP and
START condition
4.7 - 1.3 - μs
t
HD;STA
hold time (repeated) START condition 4.0 - 0.6 - μs
t
SU;STA
set-up time for a repeated START
condition
4.7 - 0.6 - μs
t
SU;STO
set-up time for STOP condition 4.0 - 0.6 - μs
t
HD;DAT
data hold time 0 - 0 - ns
t
VD;ACK
data valid acknowledge time
[1]
- 600 - 600 ns
t
VD;DAT
data valid time LOW level
[2]
- 600 - 600 ns
HIGH level
[2]
- 1500 - 600 ns
t
SU;DAT
data set-up time 250 - 100 - ns
t
LOW
LOW period of the SCL clock 4.7 - 1.3 - μs
t
HIGH
HIGH period of the SCL clock 4.0 - 0.6 - μs
t
f
fall time of both SDA and SCL signals - 300 20 + 0.1C
b
[3]
300 ns
t
r
rise time of both SDA and SCL signals - 1000 20 + 0.1C
b
[3]
300 ns
t
SP
pulse width of spikes that must be
suppressed by the input filter
- 50 - 50 ns
Fig 12. Timing diagram for serial interface
t
SP
t
BUF
t
HD;STA
PP S
t
LOW
t
r
t
HD;DAT
t
f
t
HIGH
t
SU;DAT
t
SU;STA
Sr
t
HD;STA
t
SU;STO
SDA
SCL
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