Datasheet
NXP Semiconductors
PBSS5112PAP
120 V, 1 A PNP/PNP low VCEsat (BISS) transistor
PBSS5112PAP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved
Product data sheet 30 November 2012 14 / 17
9. Package outline
10-05-31Dimensions in mm
0.04
max
0.65
max
0.77
0.57
(2×)
0.54
0.44
(2×)
2.1
1.9
2.1
1.9
1.1
0.9
0.3
0.2
0.65
(4×)
0.35
0.25
(6×)
43
1 6
Fig. 20. Package outline DFN2020-6 (SOT1118)
10. Soldering
sot1118_fr
Dimensions in mm
solder paste
solder resist
occupied area
solder lands
0.49 0.49
0.650.65
0.875
0.875
2.25
0.35
(6×)
0.3
(6×)
0.4
(6×)
0.45
(6×)
0.72
(2×)
0.82
(2×)
1.05
(2×)
1.15
(2×)
2.1
Fig. 21. Reflow soldering footprint for DFN2020-6 (SOT1118)
11. Revision history
Table 8. Revision history
Data sheet ID Release date Data sheet status Change notice Supersedes
PBSS5112PAP v.1 20121130 Product data sheet - -