Datasheet

NXP Semiconductors
PBSS4112PANP
120 V, 1 A NPN/PNP low VCEsat (BISS) transistor
PBSS4112PANP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved
Product data sheet 29 November 2012 2 / 21
Symbol Parameter Conditions Min Typ Max Unit
TR2 (PNP)
R
CEsat
collector-emitter
saturation resistance
I
C
= -500 mA; I
B
= -50 mA; pulsed;
t
p
≤ 300 µs; δ ≤ 0.02 ; T
amb
= 25 °C
- - 440 mΩ
2. Pinning information
Table 2. Pinning information
Pin Symbol Description Simplified outline Graphic symbol
1 E1 emitter TR1
2 B1 base TR1
3 C2 collector TR2
4 E2 emitter TR2
5 B2 base TR2
6 C1 collector TR1
7 C1 collector TR1
8 C2 collector TR2
Transparent top view
6
7 8
5 4
1 2 3
DFN2020-6 (SOT1118)
sym139
B1
E1
C2
B2C1
TR1
TR2
E2
3. Ordering information
Table 3. Ordering information
PackageType number
Name Description Version
PBSS4112PANP DFN2020-6 plastic thermal enhanced ultra thin small outline package; no
leads; 6 terminals; body 2 x 2 x 0.65 mm
SOT1118
4. Marking
Table 4. Marking codes
Type number Marking code
PBSS4112PANP 2T
5. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Per transistor; for the PNP transistor with negative polarity
V
CBO
collector-base voltage open emitter - 120 V
V
CEO
collector-emitter voltage open base - 120 V