Datasheet

Philips Semiconductors Product specification
80C51/87C51/80C52/87C52
80C51 8-bit microcontroller family
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
2000 Aug 07
8
Table 1. 80C51/87C51/80C52/87C52 Special Function Registers
SYMBOL DESCRIPTION
DIRECT
ADDRESS
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
MSB LSB
RESET
VALUE
ACC* Accumulator E0H E7 E6 E5 E4 E3 E2 E1 E0 00H
AUXR# Auxiliary 8EH – – – – – – – AO xxxxxxx0B
AUXR1# Auxiliary 1 A2H – – – LPEP
2
WUPD 0 – DPS xxx000x0B
B* B register F0H F7 F6 F5 F4 F3 F2 F1 F0 00H
DPTR: Data Pointer (2 bytes)
DPH Data Pointer High 83H 00H
DPL Data Pointer Low 82H 00H
AF AE AD AC AB AA A9 A8
IE* Interrupt Enable A8H EA – ET2 ES ET1 EX1 ET0 EX0 0x000000B
BF BE BD BC BB BA B9 B8
IP* Interrupt Priority B8H – – PT2 PS PT1 PX1 PT0 PX0 xx000000B
B7 B6 B5 B4 B3 B2 B1 B0
IPH# Interrupt Priority High B7H – – PT2H PSH PT1H PX1H PT0H PX0H xx000000B
87 86 85 84 83 82 81 80
P0* Port 0 80H AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FFH
97 96 95 94 93 92 91 90
P1* Port 1 90H – – – – – – T2EX T2 FFH
A7 A6 A5 A4 A3 A2 A1 A0
P2* Port 2 A0H AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 FFH
B7 B6 B5 B4 B3 B2 B1 B0
P3* Port 3 B0H RD WR T1 T0 INT1 INT0 TxD RxD FFH
PCON#
1
Power Control 87H SMOD1 SMOD0 – POF GF1 GF0 PD IDL 00xx0000B
D7 D6 D5 D4 D3 D2 D1 D0
PSW* Program Status Word D0H CY AC F0 RS1 RS0 OV – P 000000x0B
RACAP2H# Timer 2 Capture High CBH 00H
RACAP2L# Timer 2 Capture Low CAH 00H
SADDR# Slave Address A9H 00H
SADEN# Slave Address Mask B9H 00H
SBUF Serial Data Buffer 99H xxxxxxxxB
9F 9E 9D 9C 9B 9A 99 98
SCON* Serial Control 98H
SM0/FE
SM1 SM2 REN TB8 RB8 TI RI 00H
SP Stack Pointer 81H 07H
8F 8E 8D 8C 8B 8A 89 88
TCON* Timer Control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H
CF CE CD CC CB CA C9 C8
T2CON* Timer 2 Control C8H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 00H
T2MOD# Timer 2 Mode Control C9H – – – – – – T2OE DCEN xxxxxx00B
TH0 Timer High 0 8CH 00H
TH1 Timer High 1 8DH 00H
TH2# Timer High 2 CDH 00H
TL0 Timer Low 0 8AH 00H
TL1 Timer Low 1 8BH 00H
TL2# Timer Low 2 CCH 00H
TMOD Timer Mode 89H GATE C/T M1 M0 GATE C/T M1 M0 00H
NOTE:
Unused register bits that are not defined should not be set by the user’s program. If violated, the device could function incorrectly.
* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
– Reserved bits.
1. Reset value depends on reset source.
2. LPEP – Low Power EPROM operation (OTP/EPROM only)