Datasheet

Philips Semiconductors Product specification
80C51/87C51/80C52/87C52
80C51 8-bit microcontroller family
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
2000 Aug 07
25
AC ELECTRICAL CHARACTERISTICS
T
amb
= 0°C to +70°C or –40°C to +85°C, V
CC
= 5 V ±10%, V
SS
= 0 V
1, 2, 3
VARIABLE CLOCK
4
16 MHz to f
max
33 MHz CLOCK
SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT
t
LHLL
14 ALE pulse width 2t
CLCL
–40 21 ns
t
AVLL
14 Address valid to ALE low t
CLCL
–25 5 ns
t
LLAX
14 Address hold after ALE low t
CLCL
–25 ns
t
LLIV
14 ALE low to valid instruction in 4t
CLCL
–65 55 ns
t
LLPL
14 ALE low to PSEN low t
CLCL
–25 5 ns
t
PLPH
14 PSEN pulse width 3t
CLCL
–45 45 ns
t
PLIV
14 PSEN low to valid instruction in 3t
CLCL
–60 30 ns
t
PXIX
14 Input instruction hold after PSEN 0 0 ns
t
PXIZ
14 Input instruction float after PSEN t
CLCL
–25 5 ns
t
AVIV
14 Address to valid instruction in 5t
CLCL
–80 70 ns
t
PLAZ
14 PSEN low to address float 10 10 ns
Data Memory
t
RLRH
15, 16 RD pulse width 6t
CLCL
–100 82 ns
t
WLWH
15, 16 WR pulse width 6t
CLCL
–100 82 ns
t
RLDV
15, 16 RD low to valid data in 5t
CLCL
–90 60 ns
t
RHDX
15, 16 Data hold after RD 0 0 ns
t
RHDZ
15, 16 Data float after RD 2t
CLCL
–28 32 ns
t
LLDV
15, 16 ALE low to valid data in 8t
CLCL
–150 90 ns
t
AVDV
15, 16 Address to valid data in 9t
CLCL
–165 105 ns
t
LLWL
15, 16 ALE low to RD or WR low 3t
CLCL
–50 3t
CLCL
+50 40 140 ns
t
AVWL
15, 16 Address valid to WR low or RD low 4t
CLCL
–75 45 ns
t
QVWX
15, 16 Data valid to WR transition t
CLCL
–30 0 ns
t
WHQX
15, 16 Data hold after WR t
CLCL
–25 5 ns
t
QVWH
16 Data valid to WR high 7t
CLCL
–130 80 ns
t
RLAZ
15, 16 RD low to address float 0 0 ns
t
WHLH
15, 16 RD or WR high to ALE high t
CLCL
–25 t
CLCL
+25 5 55 ns
External Clock
t
CHCX
18 High time 0.38t
CLCL
t
CLCL
–t
CLCX
ns
t
CLCX
18 Low time 0.38t
CLCL
t
CLCL
–t
CHCX
ns
t
CLCH
18 Rise time 5 ns
t
CHCL
18 Fall time 5 ns
Shift Register
t
XLXL
17 Serial port clock cycle time 12t
CLCL
360 ns
t
QVXH
17 Output data setup to clock rising edge 10t
CLCL
–133 167 ns
t
XHQX
17 Output data hold after clock rising edge 2t
CLCL
–80 ns
t
XHDX
17 Input data hold after clock rising edge 0 0 ns
t
XHDV
17 Clock rising edge to input data valid 10t
CLCL
–133 167 ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN
= 100 pF, load capacitance for all other outputs = 80 pF.
3. Interfacing the 87C51, 80C51, 87C52 or 80C52 to devices with float times up to 45ns is permitted. This limited bus contention will not cause
damage to Port 0 drivers.
4. Variable clock is specified for oscillator frequencies greater than 16 MHz to 33 MHz. For frequencies equal or less than 16 MHz, see 16 MHz
“AC Electrical Characteristics”, page 24.
5. Parts are guaranteed to operate down to 0 Hz. When an external clock source is used, the RST pin should be held high for a minimum of
20 µs for power-on or wakeup from power down.