Datasheet

Philips Semiconductors Product specification
8XC54/58
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
2000 Aug 07
38
AC ELECTRICAL CHARACTERISTICS
T
amb
= 0°C to +70°C or –40°C to +85°C, V
CC
= +2.7V to +5.5V, V
SS
= 0V
1, 2, 3
16MHz CLOCK VARIABLE CLOCK
SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT
1/t
CLCL
29 Oscillator frequency
5
Speed versions : 4; 5;S 3.5 16 MHz
t
LHLL
29 ALE pulse width 85 2t
CLCL
–40 ns
t
AVLL
29 Address valid to ALE low 22 t
CLCL
–40 ns
t
LLAX
29 Address hold after ALE low 32 t
CLCL
–30 ns
t
LLIV
29 ALE low to valid instruction in 150 4t
CLCL
–100 ns
t
LLPL
29 ALE low to PSEN low 32 t
CLCL
–30 ns
t
PLPH
29 PSEN pulse width 142 3t
CLCL
–45 ns
t
PLIV
29 PSEN low to valid instruction in 82 3t
CLCL
–105 ns
t
PXIX
29 Input instruction hold after PSEN 0 0 ns
t
PXIZ
29 Input instruction float after PSEN 37 t
CLCL
–25 ns
t
AVIV
5
29 Address to valid instruction in 207 5t
CLCL
–105 ns
t
PLAZ
29 PSEN low to address float 10 10 ns
Data Memory
t
RLRH
30, 31 RD pulse width 275 6t
CLCL
–100 ns
t
WLWH
30, 31 WR pulse width 275 6t
CLCL
–100 ns
t
RLDV
30, 31 RD low to valid data in 147 5t
CLCL
–165 ns
t
RHDX
30, 31 Data hold after RD 0 0 ns
t
RHDZ
30, 31 Data float after RD 65 2t
CLCL
–60 ns
t
LLDV
30, 31 ALE low to valid data in 350 8t
CLCL
–150 ns
t
AVDV
30, 31 Address to valid data in 397 9t
CLCL
–165 ns
t
LLWL
30, 31 ALE low to RD or WR low 137 239 3t
CLCL
–50 3t
CLCL
+50 ns
t
AVWL
30, 31 Address valid to WR low or RD low 122 4t
CLCL
–130 ns
t
QVWX
30, 31 Data valid to WR transition 13 t
CLCL
–50 ns
t
WHQX
30, 31 Data hold after WR 13 t
CLCL
–50 ns
t
QVWH
31 Data valid to WR high 287 7t
CLCL
–150 ns
t
RLAZ
30, 31 RD low to address float 0 0 ns
t
WHLH
30, 31 RD or WR high to ALE high 23 103 t
CLCL
–40 t
CLCL
+40 ns
External Clock
t
CHCX
33 High time 20 20 t
CLCL
–t
CLCX
ns
t
CLCX
33 Low time 20 20 t
CLCL
–t
CHCX
ns
t
CLCH
33 Rise time 20 20 ns
t
CHCL
33 Fall time 20 20 ns
Shift Register
t
XLXL
32 Serial port clock cycle time 750 12t
CLCL
ns
t
QVXH
32 Output data setup to clock rising edge 492 10t
CLCL
–133 ns
t
XHQX
32 Output data hold after clock rising edge 8 2t
CLCL
–117 ns
t
XHDX
32 Input data hold after clock rising edge 0 0 ns
t
XHDV
32 Clock rising edge to input data valid 492 10t
CLCL
–133 ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN
= 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the microcontroller to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0
drivers.
4. See application note AN457 for external memory interface.
5. Parts are guaranteed to operate down to 0Hz.