Datasheet

Philips Semiconductors Product specification
8XC54/58
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
2000 Aug 07
27
(8XC51FX and 8XC51RX+ ONLY)
CMOD Address = OD9H
Reset Value = 00XX X000B
CIDL WDTE – – – CPS1 CPS0 ECF
Bit:
Symbol Function
CIDL Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs
it to be gated off during idle.
WDTE Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it.
– Not implemented, reserved for future use.*
CPS1 PCA Count Pulse Select bit 1.
CPS0 PCA Count Pulse Select bit 0.
CPS1 CPS0 Selected PCA Input**
0 0 0 Internal clock, f
OSC
÷ 12
0 1 1 Internal clock, f
OSC
÷ 4
1 0 2 Timer 0 overflow
1 1 3 External clock at ECI/P1.2 pin (max. rate = f
OSC
÷ 8)
ECF PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables
that function of CF.
NOTE:
* User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
** f
OSC
= oscillator frequency
SU00035
76543210
Figure 17. CMOD: PCA Counter Mode Register
CCON Address = OD8H
Reset Value = 00X0 0000B
CF CR – CCF4 CCF3 CCF2 CCF1 CCF0
Bit Addressable
Bit:
Symbol Function
CF PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is
set. CF may be set by either hardware or software but can only be cleared by software.
CR PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA
counter off.
– Not implemented, reserved for future use*.
CCF4 PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CCF3 PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CCF2 PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CCF1 PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CCF0 PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
NOTE:
* User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU00036
76543210
Figure 18. CCON: PCA Counter Control Register