Datasheet

P82B96_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 10 November 2009 7 of 32
NXP Semiconductors
P82B96
Dual bidirectional bus buffer
Input logic switching threshold voltages
V
Sx
, V
Sy
input logic voltage LOW on normal I
2
C-bus
[4]
- 640 600 (see Figure 7)mV
V
Sx
, V
Sy
input logic level HIGH
threshold
on normal I
2
C-bus
[4]
700 650 - (see Figure 8)mV
dV
Sx
/dT,
dV
Sy
/dT
temperature coefficient
of input thresholds
- −2 - - - mV/K
V
Rx
, V
Ry
input logic HIGH level fraction of applied V
CC
0.58V
CC
- - 0.58V
CC
-V
V
Rx
, V
Ry
input threshold fraction of applied V
CC
- 0.5V
CC
---V
V
Rx
, V
Ry
input logic LOW level fraction of applied V
CC
- - 0.42V
CC
- 0.42V
CC
V
Logic level threshold difference
V
Sx
, V
Sy
input/output logic level
difference
V
Sx
output LOW at
0.2 mA − V
Sx
input
HIGH maximum
[2]
50 85 - 50 - mV
Thermal resistance
R
th(j-pcb)
thermal resistance from
junction to printed-circuit
board
SOT96-1 (SO8);
average lead
temperature at board
interface
- 127 - - - K/W
Bus release on V
CC
failure
V
Sx
, V
Sy
,
V
Tx
, V
Ty
V
CC
voltage at which all
buses are guaranteed to
be released
- - 1 (see Figure 9)V
dV/dT temperature coefficient
of guaranteed release
voltage
- −4 - - - mV/K
Buffer response time
[5]
T
fall delay
V
Sx
to V
Tx
,
V
Sy
to V
Ty
buffer time delay on
falling input between
V
Sx
= input switching
threshold, and V
Tx
output falling 50 %
R
Tx
pull-up = 160 Ω;
no capacitive load;
V
CC
=5V
-70- - -ns
T
rise delay
V
Sx
to V
Tx
,
V
Sy
to V
Ty
buffer time delay on
rising input between
V
Sx
= input switching
threshold, and V
Tx
output reaching 50 %
V
CC
R
Tx
pull-up = 160 Ω;
no capacitive load;
V
CC
=5V
-90- - -ns
Table 5. Characteristics
…continued
T
amb
= +25 ° C; voltages are specified with respect to GND with V
CC
= 5 V, unless otherwise specified.
Symbol Parameter Conditions T
amb
= +25 °C T
amb
= −40 °C to
+125 °C
[1]
Unit
Min Typ Max Min Max