Datasheet

P82B96_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 10 November 2009 5 of 32
NXP Semiconductors
P82B96
Dual bidirectional bus buffer
special ‘buffered LOW’ is applied to the Sx/Sy of another P82B96 that second P82B96 will
not recognize it as a ‘regular I
2
C-bus LOW’ and will not propagate it to its Tx/Ty output.
The Sx/Sy side of P82B96 may not be connected to similar buffers that rely on special
logic thresholds for their operation, for example PCA9511, PCA9515, or PCA9518. The
Sx/Sy side is only intended for, and compatible with, the normal I
2
C-bus logic voltage
levels of I
2
C-bus master and slave chips, or even Tx/Rx signals of a second P82B96 if
required. The Tx/Rx and Ty/Ry I/O pins use the standard I
2
C-bus logic voltage levels of all
I
2
C-bus parts. There are no restrictions on the interconnection of the Tx/Rx and Ty/Ry I/O
pins to other P82B96s, for example in a star or multipoint configuration with the Tx/Rx and
Ty/Ry I/O pins on the common bus and the Sx/Sy side connected to the line card slave
devices. For more details see Application Note AN255 .
8. Limiting values
[1] See also Section 10.2 “Negative undershoot below absolute minimum value”.
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages with respect to pin GND.
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage V
CC
to GND −0.3 +18 V
V
Sx
voltage on pin Sx I
2
C-bus SDA or SCL −0.3 +18 V
V
Tx
voltage on pin Tx buffered output
[1]
−0.3 +18 V
V
Rx
voltage on pin Rx receive input
[1]
−0.3 +18 V
I
n
current on any pin - 250 mA
P
tot
total power dissipation - 300 mW
T
j
junction temperature operating range
P82B96TD/S900
−40 +125 °C
T
stg
storage temperature −55 +125 °C
T
amb
ambient temperature operating −40 +85 °C