Datasheet

P82B96_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 10 November 2009 17 of 32
NXP Semiconductors
P82B96
Dual bidirectional bus buffer
edge from the master reaching the slave (Figure 15) minus the effective delay (stretch) of
the SCL rising edge (Figure 16) plus total delays in the slave's response data, carried on
SDA, reaching the master (Figure 17).
The master microcontroller should be programmed to produce a nominal SCL LOW
period = (1300 + A − B + C) ns, and should be programmed to produce the nominal
minimum SCL HIGH period of 600 ns. Then a check should be made to ensure the cycle
time is not shorter than the minimum 2500 ns. If found necessary, just increase either
clock period.
Due to clock stretching, the SCL cycle time will always be longer than
(600+1300+A+C)ns.
Example:
The master bus has an RmCm product of 100 ns and V
CCM
=5V.
The buffered bus has a capacitance of 1 nF and a pull-up resistor of 160 Ω to 5 V giving
an RbCb product of 160 ns. The slave bus also has an RsCs product of 100 ns.
The microcontroller LOW period should be programmed to
≥ (1300 + 372.5 − 482 + 472) ns, that is ≥ 1662.5 ns.
Its HIGH period may be programmed to the minimum 600 ns.
The nominal microcontroller clock period will be ≥ (1662.5 + 600) ns = 2262.5 ns,
equivalent to a frequency of 442 kHz.
The actual bus clock period, including the 482 ns clock stretch effect, will be below
(nominal + stretch) = (2262.5 + 482) ns or ≥ 2745 ns, equivalent to an allowable
frequency of 364 kHz.
Fig 18. I
2
C-bus multipoint application
P82B96
SDA
Rx
SCL
Tx
Ty
Ry
002aab994
12 V
Sx
Sy
12 V
12 V
3.3 V to 5 V
3.3 V to 5 V
P82B96
Sx Sy
SCL/SDA
P82B96
Sx Sy
SCL/SDA
P82B96
Sx Sy
SCL/SDA
P82B96
Sx SCL
Sy SDA
no limit to the number of connected bus devices
twitsted-pair telephone wires,
USB, or flat ribbon cables;
up to 15 V logic levels,
include V
CC
and GND
3.3 V 3.3 V