Datasheet

P82B96_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 10 November 2009 16 of 32
NXP Semiconductors
P82B96
Dual bidirectional bus buffer
Figure 15, Figure 16, and Figure 17 show the P82B96 used to drive extended bus wiring,
with relatively large capacitance, linking two Fast mode I
2
C-bus nodes. It includes
simplified expressions for making the relevant timing calculations for 3.3 V or 5 V
operation. Because the buffers and the wiring introduce timing delays, it may be
necessary to decrease the nominal SCL frequency below 400 kHz. In most cases the
actual bus frequency will be lower than the nominal Master timing due to bit-wise
stretching of the clock periods.
The delay factors involved in calculation of the allowed bus speed are:
A — The propagation delay of the master signal through the buffers and wiring to the
slave. The important delay is that of the falling edge of SCL because this edge ‘requests’
the data or acknowledge from a slave. See Figure 15.
B — The effective stretching of the nominal LOW period of SCL at the master caused by
the buffer and bus rise times. See Figure 16.
C — The propagation delay of the slave's response signal through the buffers and wiring
back to the master. The important delay is that of a rising edge in the SDA signal. Rising
edges are always slower and are therefore delayed by a longer time than falling edges.
(The rising edges are limited by the passive pull-up while falling edges are actively driven).
See Figure 17.
The timing requirement in any I
2
C-bus system is that a slave's data response (which is
provided in response to a falling edge of SCL) must be received at the master before the
end of the corresponding LOW period of SCL as appears on the bus wiring at the master.
Since all slaves will, as a minimum, satisfy the worst case timing requirements of a
400 kHz part, they must provide their response within the minimum allowed clock LOW
period of 1300 ns. Therefore in systems that introduce additional delays it is only
necessary to extend that minimum clock LOW period by any ‘effective’ delay of the slave's
response. The effective delay of the slaves response equals the total delays in SCL falling
Effective delay of SDA at master = 270 + 0.2RsCs + 0.7 (RbCb + RmCm) ns.
C = F; R = Ω.
Fig 17. Rising edge of SDA at slave is delayed by the buffers and bus rise times
P82B96 P82B96
SDA
Sx
local master bus
V
CCM
SDA
MASTER
I
2
C-BUS
Cs
slave bus
capacitance
Cb
buffered bus
wiring capacitance
Cm
master bus
capacitance
Rm
GND (0 V)
V
CCB
buffered expansion bus
Tx/Rx
Tx/Rx Sx
Rb Rs
I
2
C-BUS
SLAVE
V
CCS
remote slave bus
002aab993