Datasheet

P82B96_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 10 November 2009 15 of 32
NXP Semiconductors
P82B96
Dual bidirectional bus buffer
10.1 Calculating system delays and bus clock frequency for a Fast mode
system
Effective delay of SCL at slave: 255 + 17V
CCM
+ (2.5 + 4 × 10
9
C
b
)V
CCB
+ 10V
CCS
ns.
C = F; V = volts.
Fig 15. Falling edge of SCL at master is delayed by the buffers and bus fall times
P82B96 P82B96
SCL
Sx
local master bus
V
CCM
SCL
MASTER
I
2
C-BUS
Cs
slave bus
capacitance
Cb
buffered bus
wiring capacitance
Cm
master bus
capacitance
Rm
GND (0 V)
V
CCB
buffered expansion bus
Tx/Rx
Tx/Rx Sx
Rb Rs
I
2
C-BUS
SLAVE
V
CCS
remote slave bus
002aab991
Effective delay of SCL at master: 270 + RmCm + 0.7RbCb ns.
C = F; R = Ω.
Fig 16. Rising edge of SCL at master is delayed (clock stretch) by buffer and bus rise times
P82B96
Sx
local master bus
V
CCM
SCL
MASTER
I
2
C-BUS
Cb
buffered bus
wiring capacitance
Cm
master bus
capacitance
Rm
GND (0 V)
V
CCB
buffered expansion bus
Tx/Rx
Tx/Rx
Rb
002aab992