Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsInterface ICsInterface IC - analogue switches XQFN 10

1. General description

The NX3DV42 is a double-pole double-throw analog switch suitable for use as an analog

or digital multiplexer/demultiplexer. Its wide bandwidth and low bit-to-bit skew allows the

NX3DV42 to pass high-speed differential signals with good signal integrity. Its high

channel to channel crosstalk rejection results in minimal noise interference. The

bandwidth is wide enough to pass high-speed USB 2.0 differential signals (480 Mb/s). It

consist of two switches, each with two independent input/outputs (HSDn+ and HSDn)

and a common input/output (D+ or D). One digital input (S) is used to select the switch

position. When pin OE

is HIGH, the switches are turned off. Schmitt trigger action at the

select input (S) and output enable input (OE

) makes the circuit tolerant to slower input rise

and fall times across the entire V

range from 3.0 V to 4.3 V.

2. Features and benefits

 Supply voltage range from 3.0 V to 4.3 V

 4  typical ON resistance

 7.3 pF typical ON capacitance

 950 MHz typical bandwidth or data frequency

 Low crosstalk of 30 dB at 240 MHz

 Break-before-make switching

 ESD protection:

 HBM JESD22-A114F Class 3A exceeds 4000 V

 CDM AEC-Q100-011 revision B exceeds 1000 V

 HBM exceeds 12000 V for power to GND protection

 Latch-up performance exceeds 100 mA per JESD 78 Class II Level A

 Specified from 40 C to +125 C

3. Applications

 Cell phone, PDA, digital camera and notebook

 LCD monitor, TV and set-top box

NX3DV42

Dual high-speed USB 2.0 double-pole double-throw analog

switch

Rev. 3 — 13 February 2013 Product data sheet

Summary of content (19 pages)

PAGE 1
NX3DV42 Dual high-speed USB 2.0 double-pole double-throw analog switch Rev. 3 — 13 February 2013 Product data sheet 1. General description The NX3DV42 is a double-pole double-throw analog switch suitable for use as an analog or digital multiplexer/demultiplexer. Its wide bandwidth and low bit-to-bit skew allows the NX3DV42 to pass high-speed differential signals with good signal integrity. Its high channel to channel crosstalk rejection results in minimal noise interference.
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NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version NX3DV42GM 40 C to +125 C XQFN10 plastic, extremely thin quad flat package; no leads; 10 terminals; body 1.55  2.00  0.5 mm SOT1049-3 NX3DV42GU 40 C to +125 C XQFN10 plastic, extremely thin quad flat package; no leads; 10 terminals; body 1.40 x 1.80 x 0.
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NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch 7. Pinning information 7.1 Pinning +6' ' +6' *1' +6' +6' DDD 7UDQVSDUHQW WRS YLHZ Fig 2. 8 OE D+ 1 7 HSD2+ D- 2 6 HSD2- HSD1+ 5 HSD1- 4 2( GND 3 ' 10 S 9&& 6 terminal 1 index area 9 VCC NX3DV42 1; '9 aaa-001357 Transparent top view Pin configuration SOT1049-3 (XQFN10) Fig 3. Pin configuration SOT1160-1 and SOT1337-1 (XQFN10) 7.
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NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch 9. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage [1] Max Unit 0.5 +5.5 V 0.5 +5.5 V 0.5 +5.5 V VI input voltage VSW switch voltage IIK input clamping current VI < 0.5 V 50 - mA ISK switch clamping current VI < 0.
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NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground 0 V). Symbol Parameter Tamb = 40 C to +85 C Conditions Tamb = 40 C to +125 C Unit Min Typ[1] Max Min Max IS(OFF) OFF-state leakage current VCC = 4.3 V; see Figure 4 and Figure 7 - - 1 - 2 A IOFF power-off leakage current VI or VO = 0 V to 4.
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NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch DDD DDD ,&& $ VCC = 4.3 V. Fig 5. 7DPE & VCC = 4.3 V. Waveform showing the typical input leakage current versus temperature Fig 6.
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NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch 11.2 ON resistance Table 8. ON resistance At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter RON ON resistance Tamb = 40 C to +85 C Conditions Unit Min Max Min Max - 3.9 6.5 - 10  - 0.65 - - -  VI = 0.4 V; ISW = 8 mA; see Figure 9 VCC = 3.0 V RON Tamb = 40 C to +125 C Typ[1] [2] ON resistance VI = 0.
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NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch Table 9. Dynamic characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13. Symbol Parameter tdis disable time Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit Conditions Min Typ[1] Max Min Max - 3.9 25 - 30 ns 2.0 5.9 - 2.
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NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch VI S, OE input VM GND tPHZ tPZH VOH output HIGH to OFF OFF to HIGH VX VX GND switch enabled switch disabled switch enabled aaa-001361 Measurement points are given in Table 10. Logic level: VOH is the typical output voltage level that occurs with the output load. Fig 11. Enable and disable times Table 10. Measurement points Supply voltage Input Output VCC VM VI VX 3.0 V to 3.6 V 0.5VCC VCC 0.
PAGE 10
NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch VCC S HSD1- DHSD2OE VIL VI G CL RL VEXT = 0.8 V GND aaa-001363 Test circuit also applies for D+, HSD1+ and HSD2+. Test data is given in Table 11. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. VEXT = External voltage for measuring switching times. VI may be connected to S or OE. Fig 13. Test circuit for measuring switching times Table 11.
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NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch 12.3 Test circuits 0.5VCC VCC S VIL or VIH HSD1- 1 D- switch S 1 VIL 2 VIH RL switch HSD2- 2 OE VIL fi CL dB GND aaa-001360 Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads 3 dB. Test circuit also applies for D+, HSD1+ and HSD2+. Fig 14. Test circuit for measuring the frequency response when channel is in ON-state 0.5VCC 0.
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NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch 0.5VCC D+ fi 50 Ω VIL RL CHANNEL HSD1+ or ON HSD2+ V VO1 S 0.5VCC Ri 50 Ω RL HSD1 or HSD2 D CHANNEL OFF V VO2 aaa-001362 20 log10 (VO2/VO1) or 20 log10 (VO1/VO2). Fig 16. Test circuit for measuring crosstalk between switches NX3DV42 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 February 2013 © NXP B.V. 2013. All rights reserved.
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NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch 13. Package outline XQFN10: plastic, extremely thin quad flat package; no leads; 10 terminals; body 1.55 x 2.00 x 0.50 mm SOT1049-3 X B D A terminal 1 index area E A A1 c detail X C C A B C Æv Æw b 5 y y1 C 6 4 e1 e 9 b1 1 10 terminal 1 index area L1 L 0 1 Dimensions Unit(1) mm max nom min 2 mm scale A 0.5 A1 b b1 c D 0.05 0.25 0.33 1.65 0.20 0.28 0.127 1.55 0.00 0.15 0.23 1.
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NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch XQFN10: plastic, extremely thin quad flat package; no leads; 10 terminals; body 1.40 x 1.80 x 0.50 mm SOT1160-1 X A B D terminal 1 index area E A A1 A3 detail X e1 e 3 5 C C A B C v w b y y1 C L 2 6 1 7 e2 terminal 1 index area 10 L1 8 0 1 scale Dimensions Unit(1) mm max nom min 2 mm A A1 0.5 0.05 A3 b 0.25 0.127 0.20 0.15 0.00 D E 1.5 1.4 1.3 1.9 1.8 1.7 e e1 0.4 0.
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NX3DV42 NXP Semiconductors Dual high-speed USB 2.
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NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch 14. Abbreviations Table 13. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model LCD Liquid Crystal Display MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes NX3DV42 v.
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NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
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NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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NX3DV42 NXP Semiconductors Dual high-speed USB 2.0 double-pole double-throw analog switch 18. Contents 1 2 3 4 5 6 7 7.1 7.2 8 9 10 11 11.1 11.2 11.3 12 12.1 12.2 12.3 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . .