Datasheet

MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2
Freescale Semiconductor 7
Electrical characteristics
• Direct memory access (DMA) controller (DMA Engine 2)
— Four independent fully programmable DMA channels
— Concurrent execution across multiple channels with programmable bandwidth control
— Misaligned transfer capability for source/destination address
— Data chaining and direct mode
— Interrupt on completed segment, error, and chain
• DUART
— Supports 2 DUART
— Each has two 2-wire interfaces (RxD, TxD)
– The same can be configured as one 4-wire interface (RxD, TxD, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
• Serial peripheral interface (SPI)
— Master or slave support
• Power management controller (PMC)
— Supports core doze/nap/sleep/ power management
— Exits low power state and returns to full-on mode when
– The core internal time base unit invokes a request to exit low power state
– The power management controller detects that the system is not idle and there are
outstanding transactions on the internal bus or an external interrupt.
•Parallel I/O
— General-purpose I/O (GPIO)
– 56 parallel I/O pins multiplexed on various chip interfaces
– Interrupt capability
• System timers
— Periodic interrupt timer
— Software watchdog timer
— Eight general-purpose timers
• Real time clock (RTC) module
— Maintains a one-second count, unique over a period of thousands of years
— Two possible clock sources:
– External RTC clock (RTC_PIT_CLK)
– CSB bus clock
• IEEE Std. 1149.1™ compliant JTAG boundary scan
2 Electrical characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC8309. The MPC8309 is currently targeted to these specifications. Some of these specifications are
independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer
design specifications.