Datasheet

MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2
Freescale Semiconductor 67
Clocking
23.5 Core PLL configuration
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk). The following table shows the encodings for RCWL[COREPLL]. COREPLL
values not listed, and should be considered reserved.
Table 57. CSB frequency options
SPMF csb_clk : sys_clk_in Ratio
PCI_SYNC_IN(MHz)
25 33.33 66.67
csb_clk Frequency (MHz)
0010 2:1
133
0011 3:1
0100 4:1 133
0101 5:1
125 167
0110 6:1
Table 58. e300 Core PLL configuration
RCWL[COREPLL]
core_clk : csb_clk Ratio VCO Divider
0-1 2-5 6
nn 0000 n PLL bypassed
(PLL off,
csb_clk clocks core directly)
PLL bypassed
(PLL off, csb_clk clocks core directly)
00 0001 0 1:1 ÷2
01 0001 0 1:1 ÷4
10 0001 0 1:1 ÷8
11 0001 0 1:1 ÷8
00 0001 1 1.5:1 ÷ 2
01 0001 1 1.5:1 ÷ 4
10 0001 1 1.5:1 ÷ 8
11 0001 1 1.5:1 ÷ 8
00 0010 0 2:1 ÷ 2
01 0010 0 2:1 ÷ 4
10 0010 0 2:1 ÷ 8
11 0010 0 2:1 ÷ 8
00 0010 1 2.5:1 ÷ 2
01 0010 1 2.5:1 ÷ 4
10 0010 1 2.5:1 ÷ 8
11 0010 1 2.5:1 ÷ 8
00 0011 0 3:1 ÷ 2