Information

Features
MPC8308 Product Brief PowerQUICC
™
II Pro Processor, Rev. 0
Freescale Semiconductor 9
• 9.6 Kbyte jumbo frame support
• RMON statistics support
• Internal 2-Kbyte transmit and 2-Kbyte receive FIFOs per eTSEC module
• MII management interface for external PHY control and status
• Programmable CRC generation and checking
• Support for weighted round robin and strict priority queueing
• TCP/IP checksum offload for Rx and Tx
• IPv6 and Magic Packet support
• IEEE 1588 support added
• Lossless flow control support
• QoS support for 8 Rx and 8 Tx hardware queues
• Customizable per-packet rejection
• Customizable per-packet filtering/filing to 64 logical receive queues.
— Examples: 802.1p, IP TOS, Diffserv classification, TCP/UDP ports, etc.
• Layer 2 features
— VLAN insertion and deletion per frame
— 2 exact-match MAC addresses
• Increased hash table address matching
2.3.4 DDR2 Memory Controller
The MPC8308 DDR2 memory controller includes the following features:
• Single 16- or 32-bit interface supporting DDR2 SDRAM.
• Supports single-bit error correction, double-bit error detection when ECC is enabled, and error
injection
• Support for up to 266 MHz data rate
• Support for two physical banks (chip selects), each bank independently addressable
• SDRAM chip configurations up to 2-Gbit (for DDR2) devices with x8/x16/x32 data ports
• Support for one 16-bit device or two 8-bit devices on a 16-bit bus OR one 32-bit device or two
16-bit devices or four 8-bit devices on a 32-bit bus
• Support for up to 16 simultaneous open pages
• Supports auto refresh
• On-the-fly power management using CKE
• 1.8-V SSTL2 compatible I/O
2.3.5 USB Dual-Role Controller
The MPC8308 USB controller includes the following features:
• Designed to comply with USB Revision 2.0 Specification