Information

Features
MPC8308 Product Brief PowerQUICC
™
II Pro Processor, Rev. 0
Freescale Semiconductor 7
2.1 Block Diagram
A block diagram of the MPC8308 is shown in Figure 6.
Figure 6. MPC8308 Block Diagram
2.2 Chip-Level Features
The major features of the MPC8308 are as follows:
• e300 (MPC603e-based) core, which includes 16 Kbytes of L1 instruction and data caches, a
floating point unit, and performance monitor
• Single PCI Express x1 controller with integrated SerDes PHY
• Dual three-speed 10, 100, 1000 Mbps Ethernet controllers (eTSEC)
• 32/16-bit DDR2 memory controller
• Secure digital Host controller (SDHC) interface
• USB 2.0 host and device controller
• Flexible enhanced local bus controller (eLBC)
• Integrated programmable interrupt controller (IPIC)
• General Purpose DMA controller
• Single I
2
C controller
• Serial peripheral interface (SPI) controller with master and slave support
• General-purpose I/O (GPIO) port with 24 parallel I/O pins muxed on various interfaces
• System timers including a periodic interrupt timer, real-time clock, software watchdog timer, and
four general-purpose timers
• Dual UART (DUART)