Information

MPC8308 Product Brief PowerQUICC
II Pro Processor, Rev. 0
Features
Freescale Semiconductor10
Supports operation as a stand-alone USB device
Supports one upstream facing port
Supports three programmable USB endpoints
Supports operation as a stand-alone USB host controller
Supports USB root hub with one downstream-facing port
Enhanced host controller interface (EHCI) compatible
Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operation.
Low-speed operation is supported only in host mode.
Supports USB on-the-go (OTG) mode, which includes both device and host functionality when
using an external ULPI (UTMI+ low-pin interface) PHY
Supports ULPI
2.3.6 Enhanced Secure Digital Host Controller (eSDHC)
The eSDHC includes the following features:
Compatible to SD Host Controller Standard Specification version 2.0 with test event register
support
Compatible with the MMC System Specification version 4.0
Compatible with the SD Memory Card Specification version 2.0, and supports High Capacity SD
memory cards
Compatible with the SDIO Card Specification version 1.2
Designed to work with SD Memory, miniSD Memory, SDIO, miniSDIO, SD Combo, MMC,
MMCplus, and RS-MMC cards
SD bus clock frequency up to 50 MHz
Supports 1-/4-bit SD and SDIO modes, 1-/4-bit MMC mode devices
2.3.7 Enhanced Local Bus Controller (eLBC)
The MPC8308 enhanced local bus controller (eLBC) port allows connections with a wide variety of
external DSPs and ASICs. Three separate state machines share the same external pins and can be
programmed separately to access different types of devices. The general-purpose chip select machine
(GPCM) controls accesses to asynchronous devices using a simple handshake protocol. The three user
programmable machines (UPMs) can be programmed to interface to synchronous devices or custom ASIC
interfaces. Each chip select can be configured so that the associated chip interface can be controlled by the
GPCM or UPM controller. Both may exist in the same system.
The eLBC offers the following features:
Non-multiplexed 26-bit address and 16-bit data operating at up to 66 MHz
Four chip selects support four external slaves
Up to eight-beat burst transfers
16- and 8-bit port sizes are controlled by an on-chip memory controller