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Enhanced Three-Speed Ethernet Controllers

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

Freescale Semiconductor 16-115

Table 16-114 describes the fields of the TMR_PEMASK register fields for the timer.

16.5.3.10.6 Timer Status Register (TMR_STAT)

This register requires the eTSEC filer to be enabled (via RCTRL[FILREN]). When eTSEC generates an

interrupt based on the timestamp event for a received packet, the queue ID which the incoming packet will

be sent to is captured in this register. This register update is synchronized with the RXF interrupt of the

corresponding received packet. Writing 1 to any bit of this register clears it. Figure 16-115 describes the

definition for the TMR_STAT register.

Table 16-116 describes the fields of the TMR_STAT register.

16.5.3.10.7 Timer Counter Register (TMR_CNT_H/L)

The timer register (TMR_CNT_H/L) represents accurate time in terms clock ticks or in nano-seconds.

Writes to these registers will override the previous time. The register in eTSEC1 is shared for all eTSECs.

This is a read/write register. Figure 16-109 describes the definition for the TMR_CNT_H/L register.

Table 16-114. TMR_PEMASK Register Field Descriptions

Bits Name Description

0–21 — Reserved

22 TXP2EN Transmit PTP packet event 2 enable

23 TXP1EN Transmit PTP packet event 1 enable

24–30 — Reserved

31 RXPEN Receive PTP packet event enable

Offset eTSEC1:0x2_4E14 Access: Mixed

0 25 26 31

— STAT_VEC

Reset All zeros

Table 16-115. TMR_STAT Register Definition

Table 16-116. TMR_STAT Register Field Descriptions

Bits Name Description

0–25 — Reserved

26–31 STAT_VEC Timer general purpose status vector. It will store the 6-bit queue number generated by the filer. User

to decode this status vector. For example, user can encode received PTP packet message types

(Sync, Delay_req, Follow_up, Delay_resp, Management) in the filer virtual queue field.