Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-114 Freescale Semiconductor
Table 16-113 describes the fields of the TMR_PEVENT register fields for the timer.
16.5.3.10.5 Timer Event Mask Register (TMR_PEMASK)
Timer event mask register. The event mask register provides control over which possible interrupt events
in the TMR_PEVENT register are permitted to participate in generating hardware interrupts to the PIC.
All implemented bits in this register are R/W and cleared upon a hardware reset. Figure 16-108 describes
the definition for the TMR_PEMASK register.
Offset eTSEC1:0x2_4E0C Access: Read/Write
0 15
R
—
W
Reset All zeros
16 21 22 23 24 30 31
R
— TXP2 TXP1 — RXP
W
Reset All zeros
Figure 16-107. TMR_PEVENT Register Definition
Table 16-113. TMR_PEVENT Register Field Descriptions
Bits Name Description
0–21 — Reserved
22 TXP2 Indicates that a PTP frame has been transmitted and its timestamp is stored in TXTS2 register.
0 PTP packet not transmitted
1 PTP packet has been transmitted
23 TXP1 Indicates that a PTP frame has been transmitted and its timestamp is stored in TXTS1 register.
0 PTP packet not transmitted
1 PTP packet has been transmitted
24–30 — Reserved
31 RXP Indicates that a PTP frame has been received
0 PTP packet not received
1 PTP packet has been received
Offset eTSEC1:0x2_4E10 Access: Read/Write
0 15
R
—
W
Reset All zeros
16 21 22 23 24 30 31
R
— TXP2EN TXP1EN — RXPEN
W
Reset All zeros
Figure 16-108. TMR_PEMASK Register Definition