Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-113
16.5.3.10.3 Timer Event Mask Register (TMR_TEMASK)
Timer event mask register. The event mask register provides control over which possible interrupt events
in the TMR_TEVENT register are permitted to participate in generating hardware interrupts to the PIC.
All implemented bits in this register are R/W and cleared upon a hardware reset. Figure 16-111 describes
the definition for the TMR_TEMASK register.
Table 16-112 describes the fields of the TMR_TEMASK register fields for the timer.
16.5.3.10.4 Timer PTP Packet Event Register (TMR_PEVENT)
The eTSEC precision timer logic can generate interrupts upon the capture of a timestamp due to either
transmission or reception of a frame. If an event occurs and its corresponding enable bit is set in the event
mask register (PEMASK), the event also causes a hardware interrupt at the PIC. A bit in the timer event
register is cleared by writing a 1 to that bit position. Figure 16-107 describes the definition for the
TMR_PEVENT register.
Offset eTSEC1:0x2_4E08 Access: Read/Write
05678 131415
R
— ETS2EN ETS1EN — ALM2EN ALM1EN
W
Reset All zeros
16 23 24 25 26 27 31
R
— PP1EN PP2EN PP3EN
—
W
Reset All zeros
Table 16-111. TMR_TEMASK Register Definition
Table 16-112. TMR_TEMASK Register Field Descriptions
Bits Name Description
0–5 — Reserved
6 ETS2EN External trigger 2 timestamp sample event enable
7 ETS1EN External trigger 1 timestamp sample event enable
8–13 — Reserved
14 ALM2EN Timer ALM1 event enable
15 ALM1EN Timer ALM2 event enable
16–23 — Reserved
24 PP1EN Periodic pulse event 1 enable
25 PP2EN Periodic pulse event 2 enable
26 PP3EN Periodic pulse event 3 enable
27–31 — Reserved